Energy efficient communication across on-chip wires in digital CMOS

For the past half century, CMOS process scaling has followed Moore's law, approximately doubling transistor density every 18 months. While locally routed wires have generally scaled with transistor size, longer wires have scaled at a slower rate and in some cases have grown larger as chip size and complexity have increased. Wires routed for non-local communication now consume a large and increasing portion of the power, thermal and area budgets in CMOS designs. Additionally, dynamic energy expended in driving locally routed wires has become comparable to that expended in logic. The goal of this research is to investigate methods of reducing the energy required for on-chip communication, primarily through the use of low-voltage swing signaling. A network-on-chip routing architecture is presented that uses complementary architectural and low-voltage swing signaling techniques to significantly improve the latency, throughput and power of an on-chip network. On-chip signaling circuits are presented that improve the suitability of low-voltage swing signaling for short wire lengths and reduced supply voltages. Finally, a procedure for improving the energy efficiency of wire loads in digital CMOS through the automated insertion of low-voltage swing signaling circuits is presented

Rototyper: A Novel Solution to Low Cost Three Dimensional Prototyping

In the continuing effort to reduce time spent in the product development cycle many industries have realized the benefits of rapid prototyping. Within a few hours a design engineer can turn a computer model into an actual three-dimensional object allowing customers, engineers and marketing agents to evaluate a product early in the design process, permitting quick iterative design changes to be implemented concurrently with product development. Commercially available rapid prototyping devices can produce objects quickly; however the high cost of these devices limits their accessibility to the majority of potential users, including small businesses and academia. The Rototyper is a novel, prize-winning solution to extremely low cost rapid prototyping that was produced to fulfill the graduation requirements of the Oregon State University Honors College and Department of Engineering. This document serves as a reflection and final collection of works produced during the design and construction of the Rototyper

SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects

A 64-bit, 8 × 8 mesh network-on-chip (NoC) is presented that uses both new architectural and circuit design techniques to improve on-chip network energy-efficiency, latency, and throughput. First, we propose token flow control, which enables bypassing of flit buffering in routers, thereby reducing buffer size and their power consumption. We also incorporate reduced-swing signaling in on-chip links and crossbars to minimize datapath interconnect energy. The 64-node NoC is experimentally validated with a 2 × 2 test chip in 90 nm, 1.2 V CMOS that incorporates traffic generators to emulate the traffic of the full network. Compared with a fully synthesized baseline 8 × 8 NoC architecture designed to meet the same peak throughput, the fabricated prototype reduces network latency by 20% under uniform random traffic, when both networks are run at their maximum operating frequencies. When operated at the same frequencies, the SWIFT NoC reduces network power by 38% and 25% at saturation and low loads, respectively

Exploring the links between star formation and minor companions around isolated galaxies

Previous studies have shown that galaxies with minor companions exhibit an elevated star formation rate. We reverse this inquiry, constructing a volume-limited sample of \simL\star (Mr \leq -19.5 + 5 log h) galaxies from the Sloan Digital Sky Survey that are isolated with respect to other luminous galaxies. Cosmological simulations suggest that 99.8% of these galaxies are alone in their dark matter haloes with respect to other luminous galaxies. We search the area around these galaxies for photometric companions. Matching strongly star forming (EW(H{\alpha})\geq 35 \AA) and quiescent (EW(H{\alpha})< 35 \AA) samples for stellar mass and redshift using a Monte Carlo resampling technique, we demonstrate that rapidly star-forming galaxies are more likely to have photometric companions than other galaxies. The effect is relatively small; about 11% of quiescent, isolated galaxies have minor photometric companions at radii \leq 60 kpc h$^{-1}$ kpc while about 16% of strongly star-forming ones do. Though small, the cumulative difference in satellite counts between strongly star-forming and quiescent galaxies is highly statistically significant (PKS = 1.350 \times10$^{-3}$) out to to radii of \sim 100 h$^{-1}$ kpc. We discuss explanations for this excess, including the possibility that \sim 5% of strongly star-forming galaxies have star formation that is causally related to the presence of a minor companion.Comment: 7 pages, 6 figures, submitted to MNRA

SWIFT: A SWing-reduced Interconnect For a Token-based Network-on-Chip in 90nm CMOS

With the advent of chip multi-processors (CMPs), on-chip networks are critical for providing low-power communications that scale to high core counts. With this motivation, we present a 64-bit, 8×8 mesh Network-on-Chip in 90nm CMOS that: (a) bypasses flit buffering in routers using Token Flow Control, thereby reducing buffer power along the control path, and (b) uses low-voltage-swing crossbars and links to reduce interconnect energy in the data path. These approaches enable 38% power savings and 39% latency reduction, when compared with an equivalent baseline network. An experimental 2×2 core prototype, operating at 400 MHz, validates our design.National Science Foundation (U.S.) (CCF- 0811820)National Science Foundation (U.S.) (NSF Grant CCF-0811375)Microelectronics Advanced Research Corporation (MARCO)Semiconductor Research Corporation. Interconnect Focus CenterGigaScale Systems Research Cente